A typical successive approximation register (SAR) analog-to-digital converter (ADC) includes a capacitive array or capacitive digital-to-analog converter (CDAC) for performing a successive approximation of a sampled input signal. The CDAC includes a plurality of capacitors, each of which can be assigned to a bit of the digital output word of the SAR-ADC. The capacitors can be coupled on one side, which is referred to as common node. This common node can be coupled to an input of a comparator. During each conversion step, the comparator compares its input signals and provides a bit of a digital output word to a control stage (also referred to as successive approximation register SAR). The other side of the capacitors of the CDAC are then switched in accordance with the comparison result. The plurality of capacitors may be subdivided into two or more stages. The first stage may include capacitors relating to the most significant bits (MSBs) of the digital output word of the SAR-ADC. This stage is referred to as main-CDAC. The second stage may include the capacitors relating to the least significant bits (LSBs) of the digital output word of the SAR-ADC. This second stage is referred to as sub-CDAC. There may be a serial capacitor coupling the main-CDAC and the sub-CDAC for scaling the two stages for approximation steps relating to the MSBs and the LSBs, respectively. The absolute capacitance values in the two stages may be almost similar. However, in order to achieve high resolution and good linearity, the matching of the capacitance values is important.
With the typical matching constraints of capacitance values in a semiconductor (e.g. CMOS) technology, a resolution of the SAR-ADC of about 10 to 12 bit can be achieved. For higher resolution, the capacitors mismatch has to be adjusted. The digital output word of the SAR-ADC can be digitally corrected by adding or subtracting digital correction values in order to compensate static mismatch of the capacitance values. However, this approach is only applicable as long as the successive approximation process converges. Convergence means that at the end of the conversion procedure, a voltage difference at the comparator input is equal to or smaller than the value that corresponds to an LSB. Ideal convergence means that the voltage difference between the comparator inputs corresponds to a value that is smaller than +/−½ LSB. The capacitors relating to several of the LSBs (for example capacitors of the sub-CDAC) are usually not trimmed after production of the integrated circuit as they achieve sufficient matching by design measures. There are several different principles that can be applied for trimming the capacitors of the main-CDAC. One is based on laser trimming, where capacitor values are added or subtracted from the capacitor array by use of laser beam, which removes connections in a prior assembly step. Another principle is based on adding or subtracting capacitors to and from the capacitor array based on setting switches and storing the appropriate states of the switches in a memory. Both techniques may use self calibration procedures which aim to determine the amount of mismatch of the capacitors indicating the capacitance values which are to be added or subtracted from the capacitors of the main CDAC. However, both trimming or calibration procedures require a rather complex production step, which is time consuming and increases production costs.
U.S. Pat. No. 6,747,589 B2 discloses a dynamic error correction step for an SAR-ADC in order to increase speed and reduce current drive requirements of the SAR-ADCs. The basic idea consists in testing a bit decision as to whether the error remains below a maximum admissible limit. Testing and correction is performed quasi simultaneously by selectively coupling one or two additional correction capacitors of the same size as the capacitor of the tested bit. The two additional correction capacitors are switched between the reference voltages in order to add or subtract a charge value to the network, which is equivalent to a certain bit capacitor and the output of the comparator is used as an indicator of the error. The correction capacitors provide that the successive approximation process converges. However, the digital output word of the SAR-ADC is corrected by adding or subtracting single bits corresponding to the corrected position and the mismatch of the capacitance values of the capacitors is removed by trimming procedures as described above.
There are more and less significant bits in a digital output word of a SAR-ADC, and corresponding more or less significant capacitors in the CDAC. The significance of a capacitor is not strictly related to its capacitance value, but rather to its contribution to the voltage level on the comparator input (common node). This contribution can be considered as a difference voltage or voltage step ΔV on a node, typically on the common node. The more significant bits of a digital output word are determined earlier than less significant bits during the successive approximation process. Therefore, the capacitor(s) are also used in order of their significance starting with the most significant capacitor and ending with the least significant capacitor(s).
In an integrated semiconductor device, the maximum and the minimum physical size of a capacitor is limited. The upper limit is due to chip costs due to chip area and the lower limit due to technological boundaries, as minimum structure size and parasitic effects. Therefore, the minimum and maximum capacitance value of a capacitor should remain within reasonable limits.